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Amd epyc rome cpu transistors

Although the second-generation AMD EPYC Rome data center CPU was released in August, we continue to receive detailed information streams about the internal structure of the chip and how it works. The latest details of

are provided by the German website Hardwareluxx and have an in-depth understanding of the input/output matrix on the AMD Rome CPU. The title is that the Roman chip uses no less than 39.54 billion transistors, thanks to the nine-chip design called the multicip module, which adds up to 1008mm2. The

nine chips consist of a 416 square millimeter I/O chip. The chip has 8.34 billion transistors and is connected to eight computing core chips through Infinity Fabric. The size is 74 square millimeters. Each chip has 3.9 billion transistors. Each computing core array has two computing core complexes, including four Zen 2 cores. Each core has an L2 cache and a shared L3 cache.

In contrast, the current Ryzen family I/O array is relatively small at 125mm2, with only 2.09 billion transistors. Of course, this has to do with the field and performance requirements of server chips, but it highlights how AMD has incorporated powerful features into its Rome chips.

Looking closely at the I/O chip, we see that SRAM and crossbar switches occupy the center position, with PCIe Gen 4 interfaces on both sides, and on the north and south sides, we see four memory channels with 72-bit DDR4. The

PCIe interfaces are particularly interesting because they can provide up to 162 PCIe lanes, and because the bandwidth of the 4th generation technology is doubled, this reduces the need for Infinity Fabric to rely on the bus to increase the number of lanes for the configured model. Add AMD later extended family. This is the future plan in action.

We also checked the Zen 2 computing core matrix, which is the same as that used in AMD's Ryzen and EPYC processors, and will be released on the third-generation Threadripper processor.

As far as the EPYC Rome chip is concerned, AMD uses different configurations based on the number of cores, which means that although there are 8 computing cores, all computing cores may not be used. Taking the 16-core version with only four computing core chips enabled as an example, each computing core complex uses only four cores or two cores.

With EPYC Milan and EPYC Genoa already at work, AMD is ready to use core Zen 3 and Zen 4 technologies to further innovate its chiplet design, which we believe will translate into an overall increase in market share.

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